Title:
表面実装チップ
Document Type and Number:
Japanese Patent JP5431936
Kind Code:
B2
Abstract:
A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.
Inventors:
Siam, Frank Tea
Application Number:
JP2009524743A
Publication Date:
March 05, 2014
Filing Date:
August 09, 2007
Export Citation:
Assignee:
Toshiba Techno Center Co., Ltd.
International Classes:
H01L33/48; H01L21/60; H01L33/62; H01S5/022
Domestic Patent References:
| JP2006173196A | ||||
| JP2000244010A | ||||
| JP2004071655A | ||||
| JP2000077713A | ||||
| JP2006093358A | ||||
| JP2008518436A | ||||
| JP2005277372A | ||||
| JP2004356230A | ||||
| JP2007523483A | ||||
| JP2008524831A |
Attorney, Agent or Firm:
Masahiko Hinataji