Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5465958
Kind Code:
B2
Abstract:
To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.
Inventors:
Kozo Ishikawa
Masaaki Shinohara
Toshiaki Iwamatsu
Masaaki Shinohara
Toshiaki Iwamatsu
Application Number:
JP2009201594A
Publication Date:
April 09, 2014
Filing Date:
September 01, 2009
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L29/786; H01L21/336; H01L21/8234; H01L21/8244; H01L27/088; H01L27/10; H01L27/11; H01L29/78
Domestic Patent References:
| JP2008010790A | ||||
| JP2007073831A | ||||
| JP2007142392A |
Attorney, Agent or Firm:
Yamato Tsutsui