Title:
送受信方法及び受信装置
Document Type and Number:
Japanese Patent JP5479150
Kind Code:
B2
More Like This:
Inventors:
Hiroshi Suzuki
Katsutaka Imao
Katsutaka Imao
Application Number:
JP2010035417A
Publication Date:
April 23, 2014
Filing Date:
February 19, 2010
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H04J11/00; H04J1/00
Domestic Patent References:
| JP2000312193A | ||||
| JP2000138648A | ||||
| JP4284568B2 |
Other References:
田所 嘉昭,加減算を主体としたいくつかの離散フーリエ変換アルゴリズム,電子情報通信学会技術研究報告,2001年10月18日,Vol.101, No.385,pp.33-40,IE2001-88
山本 浩子 外2名,マルチレート離散フーリエ変換の特性,電子情報通信学会技術研究報告,2002年 2月25日,Vol.101, No.669,pp.23-30,CAS2001-106
Prasanthi. R. et al.,Multiplier less FFT processor architecture for signal and image processing,Intelligent Sensing and Information Processing, 2005. Proceedings of 2005 International Conference on,2005年 1月 7日,pp.326-330
Mahmud Benhamid et al.,FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Application,Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on,2006年12月 1日,pp.641-645
山本 浩子 外2名,マルチレート離散フーリエ変換の特性,電子情報通信学会技術研究報告,2002年 2月25日,Vol.101, No.669,pp.23-30,CAS2001-106
Prasanthi. R. et al.,Multiplier less FFT processor architecture for signal and image processing,Intelligent Sensing and Information Processing, 2005. Proceedings of 2005 International Conference on,2005年 1月 7日,pp.326-330
Mahmud Benhamid et al.,FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Application,Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on,2006年12月 1日,pp.641-645
Attorney, Agent or Firm:
Minoru Maeda
Youichi Yamagata
Masahiko Shinohara
Youichi Yamagata
Masahiko Shinohara
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