Title:
半導体装置
Document Type and Number:
Japanese Patent JP5493776
Kind Code:
B2
Abstract:
To provide a semiconductor device that can verify cross-talk resistance under various conditions in the earlier stage of development.
The semiconductor device includes a signal generating circuit 3, delay circuits 40, 41, 42, 43, ..., and 4m, delay circuits 50, 51, 52, 53, ..., and 5m, and selecting circuits 60, 61, 62, 63, ..., and 6m respectively provided corresponding to output buffers 70, 71, 72, 73, ..., and 7m to select any one of the signals outputted from the delay circuits 40, 41, 42, 43, ..., and 4m or the delay circuits 50, 51, 52, 53, ..., and 5m and output the signal selected to the corresponding output buffers 70, 71, 72, 73, ..., and 7m.
COPYRIGHT: (C)2011,JPO&INPIT
Inventors:
Takao Katayama
Application Number:
JP2009270255A
Publication Date:
May 14, 2014
Filing Date:
November 27, 2009
Export Citation:
Assignee:
株式会社リコー
International Classes:
H03K19/00; G01R31/28; G01R31/30; H01L21/822; H01L27/04
Domestic Patent References:
JP2007249533A | ||||
JP2009065096A | ||||
JP2003124326A | ||||
JP2002257903A | ||||
JP2008020986A | ||||
JP200618712A | ||||
JP200954916A |
Attorney, Agent or Firm:
Hideo Takino