Title:
自己参照型MRAMセルを検知するための調節可能なタイミング信号を発生するための回路
Document Type and Number:
Japanese Patent JP5502692
Kind Code:
B2
Abstract:
Controllable readout circuit (1) for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells (51) comprising a selecting device (6) for selecting one of the MRAM cells (51), and a sense circuit (4) for sourcing a sense current (IO) to measure the first and second resistance value; the sense circuit (4) comprising a sample and hold circuit (21) for performing said storing said first resistance value, and a differential amplifier circuit (19) for performing said comparing the second resistance value to the stored first resistance value; wherein the controllable readout circuit (1) further comprises a control circuit (2) adapted to provide a pulse-shaped timing signal (C charge ) with a pulse duration controlling the duration of the first read cycle and the second read cycle. The controllable readout circuit allows for controlling the duration of the first and second read cycles after completion of the MRAM cell and readout circuit fabrication.
Inventors:
Murad El Balaji
Guy Yuen
Guy Yuen
Application Number:
JP2010224559A
Publication Date:
May 28, 2014
Filing Date:
October 04, 2010
Export Citation:
Assignee:
Crocus Technology Society Anonym
International Classes:
G11C11/15
Domestic Patent References:
| JP2003510752A | ||||
| JP2002032983A | ||||
| JP2003257173A |
Attorney, Agent or Firm:
Mitsufumi Esaki
Blacksmith
Kiyota Eisho
Blacksmith
Kiyota Eisho