Title:
静電気放電保護回路及びそれを有する集積回路装置
Document Type and Number:
Japanese Patent JP5509573
Kind Code:
B2
Abstract:
An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.
Inventors:
Arakawa Masato
Toshihiko Mori
Toshihiko Mori
Application Number:
JP2008277118A
Publication Date:
June 04, 2014
Filing Date:
October 28, 2008
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L27/04; H01L21/822; H01L21/8238; H01L27/06; H01L27/092
Domestic Patent References:
| JP2006156563A | ||||
| JP2007200987A | ||||
| JP2006324385A | ||||
| JP2005354014A | ||||
| JP2007258998A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku