Title:
情報処理装置、及び、プロセッサ間通信制御方法
Document Type and Number:
Japanese Patent JP5555116
Kind Code:
B2
Abstract:
An information processing apparatus includes a plurality of processors configured to form a pipeline, a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and another processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer, and a memory configured to be accessible from each of the processors and each of the communication units.
Inventors:
Ushiku 徹
Application Number:
JP2010219520A
Publication Date:
July 23, 2014
Filing Date:
September 29, 2010
Export Citation:
Assignee:
Canon, Inc.
International Classes:
G06F13/28
Attorney, Agent or Firm:
Chikafusa Mizugaki
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