Title:
情報処理装置および割込み制御プログラム
Document Type and Number:
Japanese Patent JP5565187
Kind Code:
B2
Abstract:
A memory stores therein a program status word containing an address of data that is to be read when an interrupt process is executed. a processor determines whether or not the program status word stored in the memory is available, controls the memory to stores a determination result in the memory in association with the program status word, acquires the program status word and the determination result from the memory when the interrupt process occurs, and reads data on the basis of the address contained in the acquired program status word when the acquired determination result indicates that the program status word is available.
Inventors:
Naoto Takeishi
Satoshi Watanabe
Satoshi Watanabe
Application Number:
JP2010179561A
Publication Date:
August 06, 2014
Filing Date:
August 10, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/48; G06F9/455; G06F9/46; G06F9/50; G06F9/54; G06F11/30
Domestic Patent References:
| JP3105529A | ||||
| JP2244334A | ||||
| JP2244345A | ||||
| JP2245937A | ||||
| JP3225529A | ||||
| JP8278895A |
Foreign References:
| WO2009087159A1 |
Attorney, Agent or Firm:
Hiroaki Sakai