Title:
電鋳用の型および電鋳用の型を製造する方法
Document Type and Number:
Japanese Patent JP5623763
Kind Code:
B2
Abstract:
A top electrically conductive layer and a bottom electrically conductive layer (22) are deposited on the top and bottom of a silicon (Si) wafer (21). The wafer is secured to a substrate (23) using an adhesive layer (24). A portion of the conductive layer on top of the silicon wafer is removed and the wafer is etched towards the bottom conductive layer in the shape of the top conductive layer removal portion for forming a mould cavity (25). Independent claims are included for the following: (1) micromechanical component fabricating method; and (2) mould for fabricating a micromechanical component.
Inventors:
ピエール・クージン
クレア・ゴルフィー
ジャン−フィリップ・ティーボー
クレア・ゴルフィー
ジャン−フィリップ・ティーボー
Application Number:
JP2010057497A
Publication Date:
November 12, 2014
Filing Date:
March 15, 2010
Export Citation:
Assignee:
ニヴァロックス−ファー ソシエテ アノニム
International Classes:
C25D1/10; C25D1/00
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa