Title:
半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP5623849
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor integrated circuit device in which stability of the element characteristics can be enhanced.SOLUTION: The manufacturing method of a semiconductor integrated circuit device includes a step for forming a first oxide film 103 on the surface of a silicon substrate 101, a step for injecting impurities into a predetermined part of the silicon substrate 101 in a peripheral circuit region A2, removing the first oxide film 103 on the predetermined part and forming a second oxide film 112 on the predetermined part, a step for forming a tunnel window in the first oxide film 103 in a memory cell region A1, forming a tunnel oxide film 116 on the silicon substrate 101 exposed in the tunnel window, and forming a polysilicon film 118 for memory cells covering the tunnel oxide film 116, and a step for forming an ONO film 119 on the polysilicon film 118 for memory cells after the step for forming the second oxide film 112.
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Inventors:
篠澤 正彦
Application Number:
JP2010214223A
Publication Date:
November 12, 2014
Filing Date:
September 24, 2010
Export Citation:
Assignee:
ラピスセミコンダクタ株式会社
International Classes:
H01L27/115; H01L21/336; H01L21/8247; H01L27/10; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Minoru Maeda
Yoichi Yamagata
Masahiko Shinohara
Yoichi Yamagata
Masahiko Shinohara