Title:
ナノ構造体およびその製造方法
Document Type and Number:
Japanese Patent JP5626847
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a nanostructure, along with a method of manufacturing the same, by which a core/shell type semiconductor nano wire is laminated and a highly efficient device can be manufactured.SOLUTION: The core/shell type semiconductor nano wire is formed on a substrate vertically thereto, this semiconductor nano wire is covered by an insulator, and this insulator is removed by etching, so that a nanostructure is manufactured in which the upper part of the semiconductor nano wire is exposed. Using this nanostructure, a tunnel junction is formed in the exposed upper part of the semiconductor nano wire. By laminating a new semiconductor nano wire on this tunnel junction, a highly efficient device can be manufactured in which a short circuit is suppressed.
Inventors:
舘野 功太
章 国強
後藤 秀樹
章 国強
後藤 秀樹
Application Number:
JP2010098644A
Publication Date:
November 19, 2014
Filing Date:
April 22, 2010
Export Citation:
Assignee:
日本電信電話株式会社
International Classes:
B82B3/00; B82B1/00; B82Y20/00; B82Y30/00; B82Y40/00; H01L31/0352; H01L31/0725; H01L31/0735; H01L33/02
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Yuzo Koike
Shigeki Yamakawa
Yuzo Koike