Title:
受信回路、システム装置及び半導体記憶装置
Document Type and Number:
Japanese Patent JP5633297
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a receiving circuit capable of suppressing occurrence of a timing error.SOLUTION: A receiving circuit 40 includes a first delay circuit 42 which gives a first delay quantity to a data strobe signal DQS so that the data strobe signal DQS has a starting leading edge at a timing of satisfying a setup time and a hold time for latching starting data of a data sequence DQ. The receiving circuit 40 includes a second delay circuit 43 which gives a second delay quantity to the data strobe signal DQS so that the data strobe signal DQS has a second leading edge at a timing of satisfying a setup time and a hold time for latching third data of the data sequence DQ. The receiving circuit 40 includes a selecting circuit S1 which selects the starting data latched at the starting leading edge of a first delay signal DQS1 and the third data latched at the second leading edge of a second delay signal DQS2.
Inventors:
板倉 賀津彦
池田 紳一郎
池田 紳一郎
Application Number:
JP2010233772A
Publication Date:
December 03, 2014
Filing Date:
October 18, 2010
Export Citation:
Assignee:
富士通セミコンダクター株式会社
International Classes:
G06F12/00; G11C11/401; G11C11/407
Attorney, Agent or Firm:
Hironori Onda
Makoto Onda
Makoto Onda