Title:
集積回路およびその形成方法
Document Type and Number:
Japanese Patent JP5635425
Kind Code:
B2
Abstract:
An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction.
Inventors:
廖 忠志
Application Number:
JP2011014013A
Publication Date:
December 03, 2014
Filing Date:
January 26, 2011
Export Citation:
Assignee:
台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ．
International Classes:
H01L21/8244; H01L21/8234; H01L27/088; H01L27/10; H01L27/11; H01L29/786
Attorney, Agent or Firm:
House ON 健