Title:
検証支援プログラム、検証支援装置、および検証支援方法
Document Type and Number:
Japanese Patent JP5640790
Kind Code:
B2
Abstract:
A computer-readable medium stores therein a verification support program that causes a computer to execute a process including first detecting an assertion that evaluates to true during simulation of a circuit, the assertion being detected from an assertion group prescribing values of registers to be met by the circuit; updating, at a clock tick subsequent to a clock tick at which the assertion is detected at the first detecting, an expected value of a register, to a value of the register as prescribed by the assertion; second detecting inconsistency between the expected value that has been updated at the updating and the value of the register; determining, based on a detection result obtained at the second detecting, validity of a change in the value of the register; and outputting a determination result obtained at the determining.
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Inventors:
パリジ マチュー
岩下 洋哲
岩下 洋哲
Application Number:
JP2011027949A
Publication Date:
December 17, 2014
Filing Date:
February 10, 2011
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Attorney, Agent or Firm:
Akinori Sakai