Title:
積層型マイクロエレクトロニクスアセンブリを製造する方法及び積層型マイクロエレクトロニクスユニット
Document Type and Number:
Japanese Patent JP5645662
Kind Code:
B2
Abstract:
A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.
Inventors:
アヴシアン，オシェル
グリンマン，アンドレイ
ハンプストン，ジャイルズ
マルガリット，モティ
グリンマン，アンドレイ
ハンプストン，ジャイルズ
マルガリット，モティ
Application Number:
JP2010519950A
Publication Date:
December 24, 2014
Filing Date:
August 01, 2008
Export Citation:
Assignee:
テッセラ，インコーポレイテッド
International Classes:
H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Okuyama In addition, it is 1.
Owner field Koichi
Tetsuo Matsushima
Hidefumi Kawamura
Ayako Nakamura
Fukagawa Hidesato
Morimoto Satoshi 2
Kyoko Tsunoda
Mikinori Hirose
Owner field Koichi
Tetsuo Matsushima
Hidefumi Kawamura
Ayako Nakamura
Fukagawa Hidesato
Morimoto Satoshi 2
Kyoko Tsunoda
Mikinori Hirose