Title:
炭化珪素半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5646044
Kind Code:
B2
Abstract:
In a conventional trench-type junction FET employing a silicon carbide substrate, the proportion of surface area of the element occupied by the pn junction between the gate and the drain is large, the capacity between the gate and the drain is large, and problems are associated therewith. This invention accordingly provides a trench-type junction FET having reduced capacity between the gate and the drain, without diminishing the withstand voltage, on resistance, or gate characteristics. Specifically, a p region (4) of the gate is formed in the upper side wall of a trench (11). Further, a p region (6) that shorts the source is formed at the trench bottom. The distance between this p region (6) and the p region (4) of the gate extends in a perpendicular direction with respect to the substrate surface.
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Inventors:
清水 悠佳
横山 夏樹
横山 夏樹
Application Number:
JP2013506829A
Publication Date:
December 24, 2014
Filing Date:
March 30, 2011
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L21/338; H01L21/337; H01L29/808; H01L29/812; H02M1/08; H02M7/48
Domestic Patent References:
| JP2004063507A | 2004-02-26 | |||
| JP2003068760A | 2003-03-07 |
Foreign References:
| US20100003573A1 | 2010-01-07 |
Attorney, Agent or Firm:
Manabu Inoue
Yuji Toda
Shigemi Iwasaki
Yuji Toda
Shigemi Iwasaki