Title:
低いデューティサイクル歪みを有するレベルシフタ
Document Type and Number:
Japanese Patent JP5646571
Kind Code:
B2
Abstract:
A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
Inventors:
チュルキュ・リー
Application Number:
JP2012221192A
Publication Date:
December 24, 2014
Filing Date:
October 03, 2012
Export Citation:
Assignee:
クゥアルコム・インコーポレイテッドＱＵＡＬＣＯＭＭ ＩＮＣＯＲＰＯＲＡＴＥＤ
International Classes:
H03K19/0185
Attorney, Agent or Firm:
Masatoshi Kurata
Toshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshiro Shirane
Peak Takashi
Yukinaga Yasujiro
Naoki Kono
Sunagawa 克
Iseki Mamoru 3
Tatsushi Sato
Okada Kishi
Mihoko Horiuchi
Masanori Takeuchi
Toshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshiro Shirane
Peak Takashi
Yukinaga Yasujiro
Naoki Kono
Sunagawa 克
Iseki Mamoru 3
Tatsushi Sato
Okada Kishi
Mihoko Horiuchi
Masanori Takeuchi