Title:
高電圧垂直トランジスタのためのセグメントピラーレイアウト
Document Type and Number:
Japanese Patent JP5648191
Kind Code:
B2
Abstract:
A transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
Inventors:
ヴィジェイ パルタサラティー
ウェイン ブライアン グラボウスキー
ウェイン ブライアン グラボウスキー
Application Number:
JP2013022107A
Publication Date:
January 07, 2015
Filing Date:
February 07, 2013
Export Citation:
Assignee:
パワー・インテグレーションズ・インコーポレーテッド
International Classes:
H01L29/78
Attorney, Agent or Firm:
Sadao Kumakura
Fumiaki Otsuka
Takayoshi Nishijima
Hiroyuki Suda
Fumiaki Otsuka
Takayoshi Nishijima
Hiroyuki Suda