Title:
メモリ制御装置、及びメモリ制御方法
Document Type and Number:
Japanese Patent JP5658556
Kind Code:
B2
Abstract:
A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.
Inventors:
畑農 博
西川 建司
都市 雅彦
西川 建司
都市 雅彦
Application Number:
JP2010288176A
Publication Date:
January 28, 2015
Filing Date:
December 24, 2010
Export Citation:
Assignee:
富士通株式会社
富士通セミコンダクター株式会社
富士通セミコンダクター株式会社
International Classes:
G06F12/02; G06F17/16
Attorney, Agent or Firm:
Kenji Doi
Wood Tsunenori
Wood Tsunenori