Title:
デジタルＰＬＬ回路及びクロック生成方法
Document Type and Number:
Japanese Patent JP5703882
Kind Code:
B2
Abstract:
A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.
Inventors:
Nakamuta Hiroshi
Furuyama Yoshito
Furuyama Yoshito
Application Number:
JP2011063109A
Publication Date:
April 22, 2015
Filing Date:
March 22, 2011
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/085; H03K5/26; H03L7/08
Domestic Patent References:
| JP2000101426A | ||||
| JP9023157A | ||||
| JP2010170651A | ||||
| JP2006101268A | ||||
| JP4081126A |
Foreign References:
| US4902920 | ||||
| US20090278618 | ||||
| US20100277203 |
Attorney, Agent or Firm:
Tadahiko Ito
Akinori Yamaguchi
Akinori Yamaguchi