Title:
半導体装置及び該半導体装置のレイアウト方法
Document Type and Number:
Japanese Patent JP5711455
Kind Code:
B2
Abstract:
Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).
Inventors:
Guo judgment
Lee Doo
Lee Doo
Application Number:
JP2009261890A
Publication Date:
April 30, 2015
Filing Date:
November 17, 2009
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/82; H01L21/3205; H01L21/336; H01L21/768; H01L21/822; H01L21/8247; H01L23/522; H01L27/04; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2007194496A | ||||
| JP2006060133A | ||||
| JP2006108510A | ||||
| JP2007324299A |
Attorney, Agent or Firm:
Makoto Hagiwara