Title:
メモリ装置
Document Type and Number:
Japanese Patent JP5720552
Kind Code:
B2
Abstract:
A clock signal is supplied to a first repair flag flip-flop, a second repair flag flip-flop, a first repair data flip-flop group, and a second repair data flip-flop group to serially transfer a second repair flag and a first repair flag stored in a non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop. Subsequently, repair data stored in the non-volatile memory is serially output to the first repair data flip-flop group, and repair data of the first repair data flip-flop group and the second repair data flip-flop group is serially transferred.
Inventors:
Tatsu Matsuo
Application Number:
JP2011270039A
Publication Date:
May 20, 2015
Filing Date:
December 09, 2011
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C29/00
Domestic Patent References:
| JP5640916B1 |
Foreign References:
| US20100318843 | ||||
| US20070165467 |
Attorney, Agent or Firm:
Takayoshi Kokubun
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