Title:
半導体装置
Document Type and Number:
Japanese Patent JP5721308
Kind Code:
B2
Abstract:
A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).
Inventors:
Yuki Nakano
Application Number:
JP2008333530A
Publication Date:
May 20, 2015
Filing Date:
December 26, 2008
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L29/78; H01L29/12
Domestic Patent References:
| JP10321848A | ||||
| JP11501459A | ||||
| JP6224437A | ||||
| JP2002531940A | ||||
| JP2007221024A | ||||
| JP2001267570A | ||||
| JP2005005655A | ||||
| JP2006093430A | ||||
| JP10098188A | ||||
| JP5082792A | ||||
| JP2002043570A |
Foreign References:
| WO2007122646A1 |
Attorney, Agent or Firm:
Minoru Yoshida
Tatsuya Tanaka
Tsukasa Senba
Hiroshi Furusawa
Yasumitsu Suzuki
Nao Usui
Tatsuya Tanaka
Tsukasa Senba
Hiroshi Furusawa
Yasumitsu Suzuki
Nao Usui