Title:
メモリデバイス
Document Type and Number:
Japanese Patent JP5733997
Kind Code:
B2
Abstract:
A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed perpendicular to the active regions and are electrically coupled to the gates of the transistors. Bit lines may be formed over the active regions to provide electrical contacts to the source/drain regions. In an embodiment, the word lines may be formed of poly-silicon over a layer of dielectric material formed over the transistors. In this embodiment, the bit lines may be formed on the metal layers. The word lines and dielectric layer may have a planar or non-planar surface.
Inventors:
Lee
Application Number:
JP2011015285A
Publication Date:
June 10, 2015
Filing Date:
January 27, 2011
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing Company,Ltd.
International Classes:
H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2002313962A | ||||
| JP3016182A | ||||
| JP5021757A | ||||
| JP2004104009A | ||||
| JP2004260044A | ||||
| JP2003297957A | ||||
| JP2000195974A | ||||
| JP2001223342A | ||||
| JP2005530355A |
Foreign References:
| WO2003044868A1 |
Attorney, Agent or Firm:
Mamoru Ushiki
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