Title:
スライドウィンドウブロックベースの分岐ターゲットアドレスキャッシュ
Document Type and Number:
Japanese Patent JP5734945
Kind Code:
B2
Abstract:
A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the Branch Target Address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
Inventors:
Rodney Wayne Smith
James Norris Defender Fur
Brian Michael Stempel
Thomas Andrew Sartorius
James Norris Defender Fur
Brian Michael Stempel
Thomas Andrew Sartorius
Application Number:
JP2012268455A
Publication Date:
June 17, 2015
Filing Date:
December 07, 2012
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F9/38
Domestic Patent References:
| JP10133874A | ||||
| JP10232776A | ||||
| JP2009540439A |
Foreign References:
| EP1624369B1 | ||||
| US5530825 |
Other References:
Andre SEZNEC et al.,"Multiple-Block Ahead Branch Predictors",INRIA Rapport de recherche,フランス,INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE,1996年 3月,pages:1-27,[平成25年10月8日検索]インターネットURL:http://hal.archives-ouvertes.fr/docs/00/07/38/67/PDF/RR-2825.pdf
原 哲也 他,「SIMP(単一命令流/多重命令パイプライン)方式に基づく改良版スーパースカラ・プロセッサの構成と処理」,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,1990年 7月20日,第90巻 第144号,103頁~108頁
Eric ROTENBERG et al.,"Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching",MICRO-29.Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996. ,米国,IEEE/ACM,1996年12月,pages:24-34
原 哲也 他,「SIMP(単一命令流/多重命令パイプライン)方式に基づく改良版スーパースカラ・プロセッサの構成と処理」,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,1990年 7月20日,第90巻 第144号,103頁~108頁
Eric ROTENBERG et al.,"Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching",MICRO-29.Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996. ,米国,IEEE/ACM,1996年12月,pages:24-34
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori