非対称二重経路処理のための装置および方法

Title:

非対称二重経路処理のための装置および方法

Document Type and Number:

Japanese Patent JP5744370

Kind Code:

B2

Abstract:

According to embodiments disclosed herein, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment, the computer processor includes: (1) a decode unit for decoding instruction packets fetched from a memory holding the instruction packets, (2) a control processing channel capable of performing control operations and (3) a data processing channel capable of performing data processing operations, wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of only control instructions to be executed sequentially on the control processing channel, and wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the data processing channel.

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Inventors:

Simon Knowles

Application Number:

JP2007505614A

Publication Date:

July 08, 2015

Filing Date:

March 22, 2005

Export Citation:

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