集積回路とその方法

Japanese Patent JP5744790

B2

A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.

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JP2001160575	EVALUATION METHOD FOR FERROELECTRIC THIN FILM

Glenn B. Allers
Chen-Chun Li
Helen Lewis Minard
Daniel Joseph Wittka Badge

JP2012122801A

July 08, 2015

May 30, 2012

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LSI LOGIC CORPORATION

H01L21/8242; H01L27/10; H01L21/02; H01L27/108

JP5291526A
JP10173148A
JP8139293A
JP10209391A
JP2000124427A

Satoshi Furuya
Akihiro Onishi
Kiyoharu Nishiyama
Rei Hosoi

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