Title:
送受信システムおよび画像表示システム
Document Type and Number:
Japanese Patent JP5753656
Kind Code:
B2
Abstract:
Reception devices 20 1 to 20 N are arranged one-dimensionally in this order. The reception device 20 n has a data input buffer 21, a first clock input buffer 22 1 , and a first clock output buffer 23 1 . The first clock input buffer 22 1 buffers a clock input to the first clock terminals P 21 and P 22 , and outputs it to the first clock output buffer 23 1 . The first clock output buffer 23 1 buffers a clock input from the first clock input buffer 22 1 and outputs it from the second clock terminals P 31 and P 32 . The data input terminals P 11 and P 12 are located between the first clock terminal and the second clock terminal.
Inventors:
Seiichi Ozawa
Hironobu Akita
Hironobu Akita
Application Number:
JP2009289338A
Publication Date:
July 22, 2015
Filing Date:
December 21, 2009
Export Citation:
Assignee:
THine Electronics Inc.
International Classes:
G09G3/20
Domestic Patent References:
| JP2008216924A | ||||
| JP2009251524A | ||||
| JP822268A | ||||
| JP200029419A | ||||
| JP2001282171A | ||||
| JP2007212543A | ||||
| JP2007171592A | ||||
| JP5017348B2 | ||||
| JP5670622B2 |
Foreign References:
| WO2007035015A1 | ||||
| WO2009045029A2 | ||||
| US20080291181 | ||||
| US20090274241 |
Other References:
Richard I. McCartney, Marshall J. Bell,“A third-generation timing controller and column-driver architecture using point-to-point differential signaling”,Journal of the Society for Information Display,2005年 2月,Volume 13, Issue 2,pp.91-97
Edward YI,“Drive your large LCD with PPDS”,EE Times Asia,2008年 4月 1日,URL,http://www.eetasia.com/STATIC/PDF/200804/EEOL_2008APR01_OPT_CTRLD_TA_01.pdf?SOURCES=DOWNLOAD
Edward YI,“Drive your large LCD with PPDS”,EE Times Asia,2008年 4月 1日,URL,http://www.eetasia.com/STATIC/PDF/200804/EEOL_2008APR01_OPT_CTRLD_TA_01.pdf?SOURCES=DOWNLOAD
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshiki Kuroki
Masatoshi Shibata
Hiroto Kido
Yoshiki Kuroki
Masatoshi Shibata
Hiroto Kido