Title:
高効率の埋め込み型均一マルチコアプラットフォーム用のタイルベースのプロセッサアーキテクチャーモデル
Document Type and Number:
Japanese Patent JP5762440
Kind Code:
B2
Abstract:
The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.
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Inventors:
Philip Manet
Bertrand Rousseau
Bertrand Rousseau
Application Number:
JP2012550469A
Publication Date:
August 12, 2015
Filing Date:
January 31, 2011
Export Citation:
Assignee:
Philip Manet
Bertrand Rousseau
Bertrand Rousseau
International Classes:
G06F15/173; G06F9/30
Domestic Patent References:
| JP7234841A | ||||
| JP63257052A | ||||
| JP7577820B2 |
Attorney, Agent or Firm:
Junji Yuda
Noriyuki Takebayashi
Noriyuki Takebayashi