Title:
ＬＳＩの回路図復元装置
Document Type and Number:
Japanese Patent JP5805452
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accurately restore a circuit diagram in an arbitrary part of a layout pattern.SOLUTION: Data having a block/cell hierarchical structure, which is stored in storage units 200 and 300, is developed to display a layout pattern in a screen by a layout pattern display unit 400. A cell frame determination unit 600 determines a virtual cell frame on the layout pattern being displayed, as a circumscribed figure of a specific figure group based on a cell frame determination condition in a condition setting unit 800. A terminal point determination unit 500 determines terminal pints at intersections between the cell frame and inter-cell wiring. A circuit diagram restoration unit 700 recognizes element configuration areas with respect to figures within the cell frame on the basis of an area recognition condition and an element recognition condition in the condition setting unit 800 and recognizes elements on the basis of mutual connection relations between the respective recognized areas and the terminal points and displays connection relations of the recognized elements as a circuit diagram.
Inventors:
Kiyoshi Yamazaki
Masahiro Tamura
Narukawa Shogo
Isao Miyazaki
Hideharu Takahashi
Masahiro Tamura
Narukawa Shogo
Isao Miyazaki
Hideharu Takahashi
Application Number:
JP2011157164A
Publication Date:
November 04, 2015
Filing Date:
July 15, 2011
Export Citation:
Assignee:
Dai Nippon Printing Co.,Ltd.
Renesas Electronics Corporation
Renesas Electronics Corporation
International Classes:
G06F17/50
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| JP9114871A | ||||
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Attorney, Agent or Firm:
Hiroshi Shimura