Title:
チップパッケージビルドアップ方法
Document Type and Number:
Japanese Patent JP5806534
Kind Code:
B2
Abstract:
A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer (16) having an opening formed therein, an adhesive layer (24) having a window (26) formed therein free of adhesive material, and a die (12) affixed to the base re-distribution layer (16) by way of the adhesive layer (24), the die (12) being aligned with the window (26) such that only a perimeter of the die (12) contacts the adhesive layer (24). A shield element (20) is positioned between the base re-distribution layer (16) and adhesive layer (24) that is generally aligned with the opening formed in the base re-distribution layer (16) and the window (26) of the adhesive layer (24) such that only a perimeter of the shield element (20) is attached to the adhesive layer (24). The shield element (20) is separated from the die (12) by an air gap (36) and is configured to be selectively removable from the adhesive layer (24) so as to expose the front surface (52) of the die (12).
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Inventors:
Paul Alan McConnery
Kevin Matthew Drowshire
Scott Smith
Laura A. Principe
Kevin Matthew Drowshire
Scott Smith
Laura A. Principe
Application Number:
JP2011158524A
Publication Date:
November 10, 2015
Filing Date:
July 20, 2011
Export Citation:
Assignee:
GENERAL ELECTRIC COMPANY
International Classes:
H01L23/12; H01L27/14; H05K3/46
Domestic Patent References:
| JP2002305199A |
Attorney, Agent or Firm:
Arakawa Satoshi
Hirokazu Ogura
Toshihisa Kurokawa
Hirokazu Ogura
Toshihisa Kurokawa