Title:
半導体装置
Document Type and Number:
Japanese Patent JP5809802
Kind Code:
B2
Abstract:
The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0@x@1), a channel layer composed of InyGa1-yN (0@y@1) with compressive strain and a contact layer composed of AlzGa1-zN (0@z@1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.
Inventors:
Yuji Ando
Yasuhiro Okamoto
Kazuki Daejeon
Takashi Inoue
Nakayama Tatsumine
Hironobu Miyamoto
Yasuhiro Okamoto
Kazuki Daejeon
Takashi Inoue
Nakayama Tatsumine
Hironobu Miyamoto
Application Number:
JP2010502868A
Publication Date:
November 11, 2015
Filing Date:
March 12, 2009
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/338; H01L21/336; H01L29/778; H01L29/78; H01L29/812
Domestic Patent References:
| JP2007311733A | 2007-11-29 | |||
| JP2007165719A | 2007-06-28 | |||
| JP2008010803A | 2008-01-17 |
Foreign References:
| WO2003071607A1 | 2003-08-28 |
Attorney, Agent or Firm:
Akio Miyazaki
Masaaki Ogata
Masaaki Ogata