Title:
半導体記憶装置およびその製造方法
Document Type and Number:
Japanese Patent JP5820353
Kind Code:
B2
Abstract:
In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction.
Inventors:
Aoyama Kenji
Application Number:
JP2012181810A
Publication Date:
November 24, 2015
Filing Date:
August 20, 2012
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2011114034A | ||||
| JP2002016155A | ||||
| JP2005108915A |
Foreign References:
| US6455440 |
Attorney, Agent or Firm:
Hirohito Katsunuma
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Hakozaki Yukio
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Hakozaki Yukio
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