Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5824536
Kind Code:
B2
Abstract:
This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.
Inventors:
Tadayoshi Miyamoto
Ito Atsushi
Mori Shigeyasu
Mitsunobu Miyamoto
Yasuyuki Ogawa
Atsushi Nakazawa
Takuya Matsuo
Seiichi Uchida
Ito Atsushi
Mori Shigeyasu
Mitsunobu Miyamoto
Yasuyuki Ogawa
Atsushi Nakazawa
Takuya Matsuo
Seiichi Uchida
Application Number:
JP2013556351A
Publication Date:
November 25, 2015
Filing Date:
January 24, 2013
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L21/336; G02F1/1368; H01L21/28; H01L29/786
Domestic Patent References:
| JP2010156960A | ||||
| JP2009099944A | ||||
| JP2008040343A | ||||
| JP2011091279A | ||||
| JP2013051328A |
Foreign References:
| WO2011010415A1 |
Attorney, Agent or Firm:
Seiji Okuda
Osamu Kita
Ryoji Yamashita
Akiko Miyake
Hidetaka Okabe
Yu Tanaka
Osamu Kita
Ryoji Yamashita
Akiko Miyake
Hidetaka Okabe
Yu Tanaka