Title:
３次元半導体素子及びその製造方法
Document Type and Number:
Japanese Patent JP5825988
Kind Code:
B2
Abstract:
A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.
Inventors:
Park Naoyo
Park Jinzawa
Gold Han Soo
Zhou Zhou
Zhaoyuan tin
Park Jinzawa
Gold Han Soo
Zhou Zhou
Zhaoyuan tin
Application Number:
JP2011250543A
Publication Date:
December 02, 2015
Filing Date:
November 16, 2011
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/8247; H01L21/336; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP1098243A | ||||
| JP60200541A | ||||
| JP6291192A | ||||
| JP2009224465A | ||||
| JP2010199311A |
Foreign References:
| US20100195395 |
Attorney, Agent or Firm:
Shinya Mitsuhiro