不揮発性メモリにおけるビットライン電圧の調整

Title:

不揮発性メモリにおけるビットライン電圧の調整

Document Type and Number:

Japanese Patent JP5827450

Kind Code:

B2

Abstract:

Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a “source” bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.

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Inventors:

Bimboga, Everym

Application Number:

JP2015525483A

Publication Date:

December 02, 2015

Filing Date:

July 29, 2013

Export Citation:

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