Title:
高速ウェイクアップのための電力スイッチ加速機構
Document Type and Number:
Japanese Patent JP5828169
Kind Code:
B2
Abstract:
A method and apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit (10) includes at least one power gated circuit block (14A-14C). The power gated circuit block (14A-14C) includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block (14A-14C) is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases,. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block (14A-14C). The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.
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Inventors:
Takayanagi Toshinari
Suzuki Shingo
Suzuki Shingo
Application Number:
JP2012230297A
Publication Date:
December 02, 2015
Filing Date:
September 28, 2012
Export Citation:
Assignee:
Apple Inc.
International Classes:
G06F1/26; H01L21/822; H01L27/04
Domestic Patent References:
| JP2011199113A | ||||
| JP2010153535A |
Attorney, Agent or Firm:
Koichi Tsujii
Sadao Kumakura
Fumiaki Otsuka
Takaki Nishijima
Takeo Nasu
Sadao Kumakura
Fumiaki Otsuka
Takaki Nishijima
Takeo Nasu