Title:
テスト装置、テスト方法、プログラム及び記録媒体
Document Type and Number:
Japanese Patent JP5829420
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a test device and the like enabled to guarantee test-pattern safety in generation of a test power-considered test.SOLUTION: A test device for use in presence/absence of a failure in a logic circuit includes: means that is given an initial test cube, assigns a logic value to an initial undetermined value bit and generates an intermediate test pattern; means for determining test-pattern safety meaning that no risk bit exists if no failure occurs in a logic circuit to which a test pattern is applied; means for specifying a candidate bit possibly contributing to guaranteeing test-pattern safety; means for generating a new test cube using an input bit of the intermediate test pattern corresponding to both of the initial undetermined bit and the candidate bit as a new undetermined bit; means for generating a final test pattern by assigning a logic value to the new undetermined bit; means for determining final-test-pattern safety; and mask means for inhibiting use of a risk bit in a logic circuit test.
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Inventors:
Warm dawn
Miyase Shinpei
Enomoto Kazunari
Miyase Shinpei
Enomoto Kazunari
Application Number:
JP2011099216A
Publication Date:
December 09, 2015
Filing Date:
April 27, 2011
Export Citation:
Assignee:
Lptex Co., Ltd.
International Classes:
G01R31/3183; G06F11/22
Domestic Patent References:
| JP2005172549A | ||||
| JP2007155339A |
Attorney, Agent or Firm:
Masaki Mine
Koji Hadachi
Koji Hadachi