Title:
半導体装置および情報読出方法
Document Type and Number:
Japanese Patent JP5839201
Kind Code:
B2
Abstract:
A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states.
Inventors:
Shiigamoto Tsunenori
Application Number:
JP2013044173A
Publication Date:
January 06, 2016
Filing Date:
March 06, 2013
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11C13/00
Domestic Patent References:
| JP2012169011A |
Foreign References:
| US20060227592 |
Attorney, Agent or Firm:
Patent Business Corporation Tsubasa International Patent Office