Title:
記憶回路
Document Type and Number:
Japanese Patent JP5839477
Kind Code:
B2
Abstract:
A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.
Inventors:
Yoshimoto Kurokawa
Application Number:
JP2012064909A
Publication Date:
January 06, 2016
Filing Date:
March 22, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K3/356; H01L21/8242; H01L27/108; H01L29/786; H03K3/037
Domestic Patent References:
| JP5110392A | ||||
| JP7288448A | ||||
| JP2007103918A | ||||
| JP20114393A |