Title:
半導体装置
Document Type and Number:
Japanese Patent JP5844956
Kind Code:
B2
Abstract:
A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
Inventors:
Onose Hidekatsu
Application Number:
JP2009052476A
Publication Date:
January 20, 2016
Filing Date:
March 05, 2009
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/337; H01L21/338; H01L21/8232; H01L21/8234; H01L27/06; H01L27/088; H01L27/098; H01L29/808; H01L29/812
Domestic Patent References:
| JP200921461A | ||||
| JP2007294716A | ||||
| JP2006100403A |
Attorney, Agent or Firm:
Yamato Tsutsui
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