Title:
ラッチ構造、周波数分周器、及びそれらを動作させる方法
Document Type and Number:
Japanese Patent JP5847861
Kind Code:
B2
Abstract:
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
Inventors:
Kung Jiang
Kenneth barnet
Kenneth barnet
Application Number:
JP2014018803A
Publication Date:
January 27, 2016
Filing Date:
February 03, 2014
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K3/356
Domestic Patent References:
| JP5095281A | ||||
| JP2008136192A |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Yoshihiro Fukuhara
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi