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Title:
トランジスタの製造方法
Document Type and Number:
Japanese Patent JP5853953
Kind Code:
B2
Abstract:
According to the present invention, there is provided a process for producing a transistor having a high precision and a high quality with a high yield by selectively etching a natural silicon oxide film, and further by selectively etching a dummy gate made of silicon. The present invention relates to a process for producing a transistor using a structural body which includes a substrate, and a dummy gate laminate formed by laminating at least a high dielectric material film and a dummy gate made of silicon having a natural silicon oxide film on a surface thereof, a side wall disposed to cover a side surface of the laminate and an interlayer insulating film disposed to cover the side wall which are provided on the substrate, said process including an etching step using a specific etching solution and thereby replacing the dummy gate with an aluminum metal gate.

Inventors:
Kenji Shimada
Yuji Matsunaga
Kojiro Abe
Kenji Yamada
Application Number:
JP2012529535A
Publication Date:
February 09, 2016
Filing Date:
July 26, 2011
Export Citation:
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Assignee:
Mitsubishi Gas Chemical Co., Ltd.
International Classes:
H01L21/336; H01L21/28; H01L21/308; H01L29/423; H01L29/49; H01L29/78
Domestic Patent References:
JP2002359369A2002-12-13
JP2008047898A2008-02-28
JPH10189722A1998-07-21
JP2004502980A2004-01-29
JP2006351813A2006-12-28
JP2004221226A2004-08-05
JPH09252114A1997-09-22
JP2009152342A2009-07-09
JP2004221226A2004-08-05
JPH09252114A1997-09-22
JP2004502980A2004-01-29
JP2007214456A2007-08-23
JP2009004510A2009-01-08
JP2004206967A2004-07-22
JP2004277576A2004-10-07
JP2006351813A2006-12-28
JP2002359369A2002-12-13
JP2008047898A2008-02-28
JPH10189722A1998-07-21



 
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