Title:
半導体装置
Document Type and Number:
Japanese Patent JP5870113
Kind Code:
B2
Abstract:
A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 µm or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.
Inventors:
Naofumi Tanie
Hiroshi Shintani
Naoki Tanaka
Hiroshi Shintani
Naoki Tanaka
Application Number:
JP2013541494A
Publication Date:
February 24, 2016
Filing Date:
October 31, 2011
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L23/48
Domestic Patent References:
| JP2007531243A | ||||
| JP2010219397A |
Attorney, Agent or Firm:
Yamato Tsutsui