Title:
プリエンファシスを備えた電圧モードドライバ
Document Type and Number:
Japanese Patent JP5897038
Kind Code:
B2
Abstract:
A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.
Inventors:
Rajavel Tina Karan
Smantra Process
Smantra Process
Application Number:
JP2013547538A
Publication Date:
April 13, 2016
Filing Date:
December 20, 2011
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H03K19/0175; H03K19/0948
Domestic Patent References:
| JP2007081608A | ||||
| JP2004350273A | ||||
| JP2010283453A |
Foreign References:
| WO2009086379A1 | ||||
| US6812733 | ||||
| US20070120582 |
Attorney, Agent or Firm:
Kyozo Katayose