Title:
ストレージプログラム、ストレージシステム、ストレージ方法、及びストレージ装置
Document Type and Number:
Japanese Patent JP6369298
Kind Code:
B2
Abstract:
A storage apparatus includes a processor. The processor is configured to sequence a plurality of data pieces. The plurality of data pieces are respectively stored in a plurality of memory devices. The processor is configured to set compensation ranges to be respectively compensated by a first predetermined number of parities. The compensation ranges are respective portions of consecutive data pieces among the sequenced data pieces. The compensation ranges include a variably set number of data pieces for the respective parities. Each of the plurality of data pieces is included in a second predetermined number of compensation ranges.
Inventors:
Takao Nakao
Application Number:
JP2014230475A
Publication Date:
August 08, 2018
Filing Date:
November 13, 2014
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F3/06
Domestic Patent References:
| JP2014525188A | ||||
| JP2000207136A | ||||
| JP2006003971A | ||||
| JP2004348281A | ||||
| JP9319528A |
Foreign References:
| EP1016967A2 | ||||
| US6035373 |
Attorney, Agent or Firm:
Takeshi Hattori