Title:
半導体装置
Document Type and Number:
Japanese Patent JP6416846
Kind Code:
B2
Abstract:
A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
Inventors:
Yoshitaka Yamamoto
Tetsuhiro Tanaka
Toshihiko Takeuchi
Yamane Yasumasa
Takuyuki Inoue
Shunpei Yamazaki
Tetsuhiro Tanaka
Toshihiko Takeuchi
Yamane Yasumasa
Takuyuki Inoue
Shunpei Yamazaki
Application Number:
JP2016207817A
Publication Date:
October 31, 2018
Filing Date:
October 24, 2016
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; H01L21/8234; H01L21/8242; H01L27/088; H01L27/10; H01L27/108; H01L27/146
Domestic Patent References:
| JP2013021315A | ||||
| JP3082164A | ||||
| JP2011124360A |
Foreign References:
| US20120146713 | ||||
| US20120085998 | ||||
| US20080237687 | ||||
| WO2010106922A1 |