Title:
メモリシステムの終端トポロジー及び関連するメモリモジュール及び制御方法
Document Type and Number:
Japanese Patent JP6429097
Kind Code:
B2
Abstract:
A memory system (100) includes a memory controller (1 10) and a memory module (120), where the memory controller (110) is arranged for generating at least a first clock signal (WCK) and an inverted first clock signal (WCKB), and the memory module (120) is arranged to receive at least the first clock signal (WCK) and the inverted first clock signal (WCKB) from the memory controller (110). In addition, the memory module (120) includes a termination module (ODT1, ODT2), and the first clock signal (WCK) is coupled to the inverted first clock signal (WCKB) through the termination module.
Inventors:
Chen Nao
Application Number:
JP2017004763A
Publication Date:
November 28, 2018
Filing Date:
January 16, 2017
Export Citation:
Assignee:
MEDIATEK INC.
International Classes:
G06F13/16; G11C11/4076
Domestic Patent References:
| JP2005310153A | ||||
| JP2009520443A | ||||
| JP2003085121A | ||||
| JP2012507933A | ||||
| JP2000268565A | ||||
| JP2000187981A | ||||
| JP20158594A |
Foreign References:
| US20080112233 | ||||
| US20110075502 | ||||
| US20110128098 | ||||
| US20030067824 | ||||
| US20080291747 | ||||
| US20030043683 | ||||
| US20100109704 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki