Title:
書込電圧生成回路及びメモリ装置
Document Type and Number:
Japanese Patent JP6444803
Kind Code:
B2
Abstract:
A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.
Inventors:
Asahi Akahori
Katsuaki Matsui
Katsuaki Matsui
Application Number:
JP2015094334A
Publication Date:
December 26, 2018
Filing Date:
May 01, 2015
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G11C16/10
Domestic Patent References:
| JP7244993A | ||||
| JP2011187145A |
Foreign References:
| US5708387 |
Attorney, Agent or Firm:
Motohiko Fujimura
Shinji Takano
Shinji Takano