Title:
３次元メモリ用の単結晶シリコンを有する選択ゲートトランジスタ
Document Type and Number:
Japanese Patent JP6450888
Kind Code:
B2
Abstract:
A fabrication process for a 3D memory structure provides a single crystal silicon channel for a drain-side select gate (SGD) transistor using a laser thermal anneal (LTA). The 3D memory structure includes a stack formed from an array of alternating conductive and dielectric layers. A NAND string is formed by filling a memory hole with memory films, including a charge trapping material, a tunnel oxide and a polysilicon channel. In one case, a separate oxide and polysilicon forms the SGD transistor gate oxide and channel respectively, where LTA is performed on the polysilicon. In another case, the same oxide and polysilicon are used for the SGD transistor and the memory cells. A portion of the polysilicon is converted to single crystal silicon. A back side of the single crystal silicon is subject to epitaxial growth and thermal oxidation via a void in a control gate layer.
Inventors:
Marshed chowdhury
Yan Lee Chang
Jin Ryu
Rough Bar S. Makara
Johann Arsmeyer
Yan Lee Chang
Jin Ryu
Rough Bar S. Makara
Johann Arsmeyer
Application Number:
JP2018514397A
Publication Date:
January 09, 2019
Filing Date:
September 13, 2016
Export Citation:
Assignee:
SanDisk Technologies LLC
International Classes:
H01L27/1157; H01L21/336; H01L27/11582; H01L29/788; H01L29/792
Domestic Patent References:
| JP2013038124A |
Foreign References:
| US20140112049 | ||||
| US20120086072 | ||||
| US20150079765 | ||||
| US20140252363 | ||||
| US20140138687 | ||||
| US20110233648 |
Attorney, Agent or Firm:
Kaiyu International Patent Office
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